As line widths of complimentary metal-oxide-semiconductor (CMOS) very large scale integration (VLSI) chips decreases and operating frequency increases, capacitance loading causes increasingly large and unpredictable skew in clock pulses distributed in the chip. The uncertainty becomes unmanageable at about one micron feature size and 25 megahertz (MHz) operation because the capacitive coupling between adjacent wires becomes greater than that between a wire and the substrate at one micron and at 25 megahertz the skew is already noticeable and increasing linearly with frequency.
Although not generally recognized, adjacent electrical conductors in such VLSI chips exhibit widely varying and unpredictable capacitive loading characteristics. In a VLSI chip of 1 cm.times.1 cm, a clock distribution line can be 1.5 cm long. The capacitance of the line is about 5 picofarads (pf) in 1.25 micron technology. This capacitance is larger than the drain and fanout capacitance (estimated at 1-2 pf). Consequently, the clock distribution delay is determined primarily by the uncertain clock line capacitance. If the clock circuit design delay specification in 2 nanoseconds (NS), the uncertainties in the clock edge are in the range of 1-5 NS which is unacceptable.